Full PDK development services providing foundry-specific models, symbols, rule decks, and parameterized cells (PCells).
SPICE Models – SPICE model (optional) files, verified with the SmartSpice Circuit Simulator, at the foundry-supplied process corners (temperature, voltage, process). Silvaco will extract one set of models from a wafer or measured data and produce a complete measured vs. simulation report for each device.
Technology Files – layer files that correlate the legal GDSII layers for each of the process layers for layout and verification tools. Display files to customize the layout and schematic tools for GDS layers, display colors and user-customizable hot keys.
Rule Decks –contain the layout rules encoded into the format used by the Expert Layout Editor, Guardian DRC /LVS/LPE tools, and the Hipex Full-chip Parasitic Extractor.
Parameterized Cells – enable annotated device schematics to be automatically drawn in the ExpertLayout Editor, DRC and LVS correct, using the LISA scripting language.
|B. PCells are instantiated by Expert Layout Editor with flight lines and placed to final layout.||C. SmartSpice simulates extracted bandgap over temperature.|