IC layout, DRC/LVS verification, and RC parasitic extraction environment for analog, mixed-signal and RF design engineers
Schematic Editor and Schematic Viewer. Supports flat or hierarchical designs of any technology. Gateway readily accepts legacy designs from other schematic editors through EDIF 2 0 0 standard.
DRC/LVS/NET Physical Verification. Provides interactive and batch mode verification of analog, mixed signal and RF IC designs.
Layout Editor. Hierarchical IC layout editor with full editing features, large capacity and fast layout viewing.
Full-Chip Parasitic Extraction.Performs extraction of parasitic capacitances and resistances from hierarchical layouts.