Digital tools for cell library characterization, large core STA, Verilog simulation, fault analysis, placement and routing.
Mixed-Level Fault Simulator.Verilog IEEE-1364-2001 compliant fault simulator that analyzes test vectors’ ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing.
SPICE Netlist to Verilog Gates Converter. The premier tool for converting transistor-level designs into verilog gate-level representations with applications in microprocessor, DSP, graphics and high-speed communication markets.
Verilog Simulator. Easy-to-use IEEE-1364-2001 compliant Verilog simulator. An industry standard since 1986, its debugging features provide a productive design environment for FPGA, PLD, ASIC and custom digital designs.